The present invention relates generally to the fabrication of semiconductor devices, and more particularly to the fabrication of magnetic random access memory (MRAM) devices.
Semiconductors are widely used for integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. One type of semiconductor device is a semiconductor storage device, such as a dynamic random access memory (DRAM) and flash memory, which use a charge to store information.
Spin electronics combines semiconductor technology and magnetics, and is a more recent development in memory devices. In spin electronics, the spin of an electron, rather than the charge, is used to indicate the presence of a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. One such spin electronic device is an MRAM device, which includes conductive lines positioned in different directions to one another in different metal layers, the conductive lines sandwiching a magnetic stack or magnetic memory cell. The place where the conductive lines, e.g., wordlines and bitlines, intersect is called a cross-point. A current flowing through one of the conductive lines generates a magnetic field around the conductive line and orients the magnetic polarity into a certain direction along the wire or conductive line. A current flowing through the other conductive line induces a magnetic field and can partially turn the magnetic polarity, also. Digital information, represented as a xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, is storable in the alignment of magnetic moments. The resistance of the magnetic component depends on the moment""s alignment. The stored state may be read from the element by detecting the component""s resistive state.
A memory cell array is generally constructed by placing the conductive lines and cross-points in a matrix structure having rows and columns. Information is stored in the soft magnetic layer or free layer of magnetic stacks. To store the information, a magnetic field is necessary. This magnetic field is provided by a wordline and bitline current which is passed through the conductive lines. The information is read by applying a voltage to the particular cell to be read, and determining the resistance value of the cell, which indicates a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d logic state.
An advantage of MRAM devices compared to traditional semiconductor memory devices such as DRAM devices is that MRAM devices are non-volatile. For example, a personal computer (PC) utilizing MRAM devices would not have a long xe2x80x9cboot-upxe2x80x9d time as with conventional PCs that utilize DRAM devices. Also, an MRAM device does not need to be powered up and has the capability of xe2x80x9crememberingxe2x80x9d the stored data. MRAM devices have the potential to eliminate the boot up process, store more data, access that data faster and use less power than current memory technologies.
In the manufacturing of MRAM devices, typically, a memory cell typically comprises a magnetic stack including a plurality of metals with a thin layer of dielectric therebetween. The magnetic stack may have a total thickness of a few tens of nanometers, for example. For cross-point MRAM structures, the magnetic stack is usually located at the intersection of two metal wiring levels, for example, at the intersection of metal 2 (M2) and metal 3 (M3) layers that run in different directions positioned at an angle to one another. The tops and bottoms of the magnetic stacks typically contact the M(n) and M(n+1) wiring layer conductive lines, respectively.
In a cross-point MRAM devices, the magnetic tunnel junction (MTJ) cells are located at the cross-points of first and second conductive lines, e.g., wordlines and bitlines. The wordlines and bitlines create a magnetic field when a write current is passed through them. The MTJ cells include a hard or reference layer comprised of one or more magnetic layers, an insulating layer referred to as a tunnel barrier or tunnel junction, which has resistive properties, and a free or soft layer, also comprised of one or more magnetic layers. The magnetic fields from both the wordline and bitline add up, resulting in switching the memory cell by changing the resistance of the tunnel barrier. In this manner, cells are selected for switching in a cross-point array.
A problem with prior art MRAM designs is that because a magnetic field is used to write the cells, there is a risk of switching undesired, for example, memory cells adjacent the targeted memory cell, due to inconsistencies in the magnetic material properties of the cells, for example. Also, any memory cell that is disposed over the same word or bit line as the selected cell sees a portion of the magnetic switching field and may be inadvertently switched, for example. Other causes of undesired switching of cells may include fluctuations in the magnetic field, or alterations in the shape of the field, as examples. Therefore, a write margin is desired for switching the cells without error.
An alternative cell selection concept that has been proposed in MRAM technology utilizes a field-producing current on the bit line and a heating current to reduce saturation magnetization for the selected cells. In this heated cell selection method, only the heated cells can be switched, improving the write margin and reducing the chances of unintended cells being written. For this thermal select concept, running a heat current from the wordline to the bitline through the tunnel junction has been proposed, using the tunnel junction basically as a heating resistor. However, the insulating material used for the tunnel barrier typically cannot withstand the high current passed through it in this scheme, resulting in damage to the tunnel junction and thus, destruction of the memory cell.
What is needed in the art is a reliable structure and method for thermally selecting magnetic memory cells of MRAM devices that does not damage the tunnel barrier.
Preferred embodiments of the present invention achieve technical advantages by providing an MRAM layout and thermal selection for memory cells wherein the memory cell free layer acts as a heat resistor. Wordlines with gaps over the centers of the memory cells are utilized to run a heat current to a row of memory cells, allowing the thermally selection of the heated row of memory cells. A cap layer may be disposed over each memory cell, wherein a portion of the heat current is adapted to be run through the cap layer to provide the write current for the hard axis field of the selected row of cells.
In one embodiment, a resistive semiconductor memory device is disclosed, comprising a plurality of first conductive lines running in a first direction, and a plurality of magnetic memory cells disposed over the first conductive lines. The resistive semiconductor memory device includes a plurality of second conductive lines running in a second direction disposed over the magnetic memory cells, the second direction being different from the first direction, wherein the second conductive lines are non-continuous.
In another embodiment, a method of fabricating a resistive semiconductor memory device is disclosed. The method includes providing a workpiece, disposing a plurality of first conductive lines over the workpiece, and forming a plurality of magnetic memory cells over the first conductive lines. Forming the magnetic memory cells includes forming a first magnetic layer over the first conductive lines, forming a tunnel barrier layer over the first magnetic layer, depositing a second magnetic layer first material over the tunnel barrier, and depositing a second magnetic layer second material over the second magnetic layer first material. The second magnetic layer second material has a lower Curie temperature than the Curie temperature of the second magnetic layer first material. The method includes forming a plurality of second conductive lines over the magnetic memory cells, wherein the second conductive lines are non-continuous and have gaps over central portions of the magnetic memory cells.
In another embodiment, a method of writing to an MRAM device is disclosed. The method includes providing an MRAM device having an array of magnetic memory cells disposed over a plurality of first conductive lines. The memory cells include a soft layer including a first magnetic material and a second magnetic material disposed over the first magnetic material, where the second magnetic material has a lower Curie temperature than the first magnetic material. The MRAM device includes a plurality of non-continuous second conductive lines disposed over the magnetic memory cells. According to an embodiment of the method, a heat current is run through at least a portion of one of the second conductive lines through the second magnetic material of at least one of the magnetic memory cells, wherein the heat current increases the temperature of the second magnetic material.
Advantages of embodiments of the invention include increasing the write margin of resistive memory devices. A row of memory cells may be thermally selected, using the soft or free layer as the resistive heating element. No additional wiring or material layers are necessary in accordance with embodiments of the invention. The heat current is applied to the row using the second conductive lines, e.g., wordlines disposed adjacent the soft layer. A cap layer may be disposed over the memory cells through which a portion of the current may be run, to provide the write current for the hard axis field of the magnetic memory cells. The required write currents for both wordlines and bitlines are reduced in accordance with embodiments of the invention.